Assertion:
               Assertions are used to validate the behaviour of the design.There are 2 kinds of assertions .
              1) Concurrent assertion .
              2) Immediate assertion .

Concurrent assertion:
           a) Based on clock cycle. (Note:Simulation tick event < Clock cycle)
           b) Sampling of variables is done in the "preponed" region and the evaluation of the
               expression is done in the "observed" region of the scheduler.[Note: its mostly an EDA tool                   stuff]
          c) The keyword “property” differentiates the concurrent assertions from immediate
              assertions.
          d) Can be coded in a procedural block like a module, an interface or a program blocks
               definitions.
Immediate assertion:
         a) Based on simulation event semantics.
         b) Test expression is evaluated within a procedural block. These are not temporal in
              nature and are evaluated immediately.

Example:
//------------------------------------------------------------------------------
// Module name: test
// Description:
//------------------------------------------------------------------------------
`timescale 1ns/1ns
module test;
  
//Variable declaration 
reg clk,x,y;
//procedural block
always 
begin
      clk <= 0;
      #3;
      clk <= 1;
      #2;
end

//Immediate assertion
always @(*)
   IA_chk: assert (x && y == 1'b1) $info("%m IA_INFO:BOTH ARE HIGH"); 
                   else $info("%m IA_INFO:BOTH ARE NOT HIGH");
                     
//Concurrent assertion 
  CA_chk: assert property (@(posedge clk) (x && y == 1)) $info("%m CA_INFO:BOTH ARE HIGH");
                 else $info("%m CA_INFO:BOTH ARE NOT HIGH");
   
//Testcase 
initial 
begin
  for(int j=0;j<10;j=j+1) begin
    #1;
    x <= ($random%2);    // ($random)%2 = singed ; ($random%2) = unsinged 
    #1;
    y <= (($random%2)==1) ? 0:1;
    y <= #500ps 1;             
    #($random%3);
    y <= (($random%2)==1) ? 1 : y;
    #2;
  end
end
endmodule:test

Waveform1

In the above waveform1,
IA_chk fail count is 4.Whenever the input x && y is not equable to 1 and change in input x and y the assertions triggered .
CA_chk:fail count is 1.Only on  the raising edge of clk the assertions is triggered.

Question for discussion :
   When to use  immediate assertion? When to use concurrent assertion ?